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71M6545/71M6545H Data Sheet
SPI Commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is shown in the
SPI Transactions description.
2.5.13 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6545/H. It uses the
RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET pin
were pulled high, except that the I/O RAM bits are in the same state as after a wake-up from SLP mode
(see the I/O RAM description in 5.2 for a list of I/O RAM bit states after RESET and wake-up). Four
thousand, one hundred CK32 cycles (or 125 ms) after the WDT overflow, the MPU is launched from
program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0. The WDT is disabled when the
ICE_E pin is pulled high.
2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins.
One of the digital or analog signals listed in Table 53 can be selected to be output on the TMUXOUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX[4:0] (I/O RAM 0x2502[4:0] , as
shown in Table 53 .
One of the digital or analog signals listed in Table 54 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]) , as
shown in Table 54.
The TMUX and TMUX2 I/O RAM locations are non-volatile and their contents are preserved by
battery power and across resets.
The TMUXOUT and TMUX2OUT pins may be used for diagnosis purposes or in production test. The
RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides
even higher precision.
Table 53: TMUX[4:0] Selections
TMUX[5:0]
1
9
A
D
E
Signal Name
RTCLK
WD_RST
CKMPU
V3AOK bit
V3OK bit
Description
32.768 kHz clock waveform
Indicates when the MPU has reset the watchdog timer. Can be
monitored to determine spare time in the watchdog timer.
MPU clock – see Table 8
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M6545/H monitors the V3P3A pin voltage only.
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654 monitors the V3P3A pin voltage only.
1B
1C
1D
1F
MUX_SYNC
CE_BUSY interrupt
CE_XFER interrupt
RTM output from CE
Internal multiplexer frame SYNC signal. See Figure 4
Figure 5 .
See 2.3.3 on page 25 and Figure 12 on page 45
See 2.3.5 on page 26
and
Note:
All TMUX[5:0] values which are not shown are reserved.
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